In quarter 10 the production run was finally completed, and eight boards were delivered at Astron/Jive, a momentous occasion. After extensive testing the boards were distributed to the partners.

Obviously, the testing and validation of the hardware took priority at JIVE and ASTRON. Documentation for the integrated test firmware was written, to be included in the shipment, images loaded on all boards, and all boards were integrated with XGBs and enclosures. An issue tracking system was also set up to streamline the handling of software/hardware issues. At the end of the quarter, all partners had received their boards, although KASI experienced problems with Korean customs. The ShAO board remained at JIVE, and will be taken to China when two visiting ShAO digital engineers return home in October 2011.

Documents

• UniBoard 2: Delivery package and recommended peripherals Gijs Schoonderbeek, 25-05-2011
• UniBoard digital receiver revised design doc Gianni Comoretto, et al., 05-04-2011
• EVN Correlator Design revised March 2011. Jonathan Hargreaves, Harro Verkouter, 01-04-2011
• UniBoard rev 2.0 Firmware Built-In-Self-Test. Eric Kooistra, 26-05-2011
• UniBoard Firmware Platform. Eric Kooistra, 26-05-2011
• Controlling the UniBoard from Erlang/tips about Erlang (vs 1.0). Harro Verkouter, 03-06-2011

General activities in Q10:

• Monthly project-wide general telecons
• One JIVE/ASTRON Correlator Implementation and Control meeting
• 2-weekly ASTRON/JIVE internal technical meetings
• 2-weekly internal technical meetings at UMAN
• Two UMAN-UORL telecons

Activities by institute in Q10:

ASTRON:

• 8 boards produced and delivered, tested
• (with JIVE) Integrated test firmware completed, loaded on boards
• (with JIVE) Documentation for integrated test firmware written
• Boards integrated with XGB and metal enclosures
• Systems shipped to partners
• Issue tracking system set up

BORD:

• Tests conducted for setting up communication between python/erlang TCP client/server

INAF:

• Functional testing of complete design (excluding UDP formatting)
• Integration of simple test core in the SOPC UniBoard structure
• Test of the communication with the physical board

JIVE:

• (with ASTRON) Integrated test firmware completed, loaded on boards
• (with ASTRON) Documentation for integrated test firmware writte n

EVN Correlator Design:

• Firmware modules for the 10Gbps ethernet ports, VDIF decoder, Polyphase Filter Bank and FN-BN Interface were integrated into the top level front node design
• The FN design was simulated to generate a stimulus file which can be used to verify the back node design

Board control:

• Creation of a test framework in Erlang, allowing board tests and their results to be run and displayed in a consistent manner
• Research of network throughput from the Erlang control software to the UniBoard FPGAs. Dependency of this quantity as a function of number of CPU cores, CPU speed, packet size and number of simultaneously addressed FPGAs was investigated as well as the effect of different NiosII CPUs
• Fixing and modification of existing Erlang drivers, as well as addition of new drivers

KASI:

• Provided documentation of the UniBoard prototype for customs

UMAN:

• Implementation and testing of a 2 x 10G UDP frame loopback test harness based on a STRATIX IV eval board, and standard Altera 10G IP, mounted in a PC
• Implementation of dummy DSP block and frame pass through loop test
• Installation of UniBoard in rack, purchased and installed power supply
• Diagnosis of UniBoard BIST failure
• Completed configuration of board using JTAG and basic bit-map
• Used Erlang tools to establish communication with board
• Verification of ability to request and read back on-board temperature
• Design and implmentation of FFT architecture for large transforms
• Building of test bench system on a Berkeley ROACH board, only used for simple tests
• Work on generator of coefficients needed for coherent dedispersion

UORL:

• Extension of the one channel RFI detectors to the multi channel case (design and simulation)
• Update of our documents after an internal review
• Basic tests of uniboard functionalities

UOXF:

• No input received

SHAO:

• Development of a small e-VLBI correlator using the dBBC PCB as test bed
• VHDL core will be moved to UniBoard
• System design of backend of new 65 meter telescopes started, based on UniBoard

Problems/issues

• The Correlator Front Node (FN) design with 8 filterbanks proved difficult for Quartus to fit in the chip. For now the design has been reduced to 4 filterbanks so that hardware testing of the complete design can proceed.
• The FN simulation was truncated after 5 FFT periods due to an error in the Altmemphy DDR3 controller. Longer simulations are possible using the newest, Quartus v11 UniPhy DDR3 controller, so this will be used in both the FN and BN designs

Red flags - major problems

• none

Forward look

ASTRON:

• 8-10 UniBoards will be ordered for Apertif, AARTFAAC and ShAO
• Completion of design of a clock board, needed to integrate multiple UniBoards on a backplane
• Design of a subrack to hold multiple boards
• Design of a backplane
• Integration of Apertif A/D conversion unit with the UniBoard
• For Apertif: firmware to capture and filter ADU data and beamform them over multiple antenna elements

BORD:

• Test of the uniboard hardware delivered to the Bordeaux team.
• Test of the dbbc design
• Preparation of ADC-based tests

INAF:

• Completion of remaining FPGA modules (UDP formatting)
• Integration of cores in common SOPC Uniboard structure
• Test of the individual cores on the physical board using internally generated signals
• Initial development and testing of control software

JIVE:

• July-Aug 2011: Integrate FN-BN interface, corner turner and correlator engine into top level BN design
• Sept 2011: Hardware testing of FN and BN designs (Autocorrelations)
• Sept-Dec 2011: Integrate delay module and test design with real data
• Jan-Mar 2012: Expand operating modes, increase power efficiency
• A second Erlang lecture for the project partners is in the planning. This time it will be an interactive tutorial focusing only on the UniBoard

SHAO:

• In Q11 - Q12 two engineers from ShAO will visit Jive/Astron for an extended period, to gain familiarity with the UniBoard architecture and Altera development tools
• Porting of locally developed VHDL cores to UniBoard

UMAN:

• Transfer implmentations produced for the test board across to the Uniboard for the UDP frames and block transfer
• Continuation of work on implementation of UniBoard NIOS 2 based Control Plane processor and associated Erlang control code.
• Test of FFT architecture, coefficients generator and folding on the test system, turn into a full pipeline
• Detailed testing of this architecture on UniBoard itself
• Implement test bench for the already developed Taylor tree dedispserion architecture

UORL:

• Face to face meeting (one week in Nancay) with UMAN in September to define the interface between the two designs
• Hardware tests of design with fake data on one Altera FPGA
• Hardware tests on Uniboard
• Paper on RFI mitigation for pulsar observation with UniBoard in a French technical magazine

Expected milestones/ deliverables

All deliverables are in place, the next and final deliverables are due in month 36.