UniBoard achievements in Q1 + Q2
With all its manpower in place from the very beginning of the project, ASTRON has made excellent progress, and at the end of Q2 the schematic design of the board is ready to be reviewed. JIVE has mobilized several of its staffmembers to narrow down the hardware requirements for a next generation EVN correlator (by far the most demanding application of the project). With the hiring of a full-time digital engineer during Q2 the VHDL design effort at JIVE is also taking shape. INAF and BORD have made good progress with the digital receiver design, as has UORL with RFI mitigation work for the pulsar binning machine. Due to a heavy workload at Manchester, the UMAN group has not been able to start the actual work, although they have participated in meetings and discussions. This situation is about to improve, and a UMAN-UORL meeting is planned. KASI finally will only get involved during the hardware test phase, and may second an engineer for an extended period to assist the ASTRON engineers.
After careful discussions, both with vendors and partners, a choice was made for Altera FPGAs (in Q2). This choice was made both on the grounds of availability (the only competitor, Xilinx, would not be able to deliver a comparable product on the right timescale), cost and architecture. Even so, the total price of the boards will exceed the hardware budget, so all partners have agreed to pay an additional subsidy to the project, before delivery. An MOU to this effect is being drafted now (end of Q2).
Working documents:
UniBoard for EVN: Block diagram and analysis Gijs Schoonderbeek, 13-3-2009
UniBoard digital receiver design (draft) Gianni Comoretto, et al., 08-2-2009
Draft for e-VLBI correlator, Paul Boven, 2009-03-13
Draft discussion document re. Control Software Frameworks, Harro Verkouter, 2009-03-23
UniBoard board design, Gijs Schoonderbeek, Sjouke Zwier, 29-5-2009
Uniboard firmware development, Eric Kooistra, 5-06-2009
Uniboard SVN draft database structure, Eric Kooistra, 24-06-2009
General activities in Q1:
UniBoard kick-off meeting, Dwingeloo, February 26th - February 27th
2-weekly general telecons
Meeting with KASI representatives in Dwingeloo directly following RadioNet FP7 kickoff meeting
Activities by institute in Q1:
ASTRON:
2-weekly ASTRON internal meetings
Start of the system design for UniBoard
Start of Hardware design for UniBoard
Comparing the major FPGA players (Altera and Xilinx)
Exploring PCB capabilities
Exploring IO capabilites (optical 10GbE interface)
Exploring Development platform (Modelbased design)
BORD:
Work on the mathematical model of the filter bank design which includes the polyphase filter + 64 point FFT
The model is electronic structure oriented in view of the actual design. Only a full scale representation was used so far; the quantization effect study is ongoing.
In parallel, but relevant to the development of UniBoard, work on a new fast ADC continued (A. Baudry and P. Cais  with several other people not directly involved in UniBoard). Design of a Track/Hold circuit (65 nano techno) has been completed and sent to the foundry.
INAF
Conceptual design of the Digital Receiver filterbank
Draft design document, describing the structure and the general performances of the proposed design
Resource estimate using simplified conceptual VHDL coding
JIVE:
series of 4 2-weekly meetings with presentations on various software solutions for building a correlator control system
regular meetings with ASTRON to narrow down specific hardware demands posed by EVN correlator application
creation of web-based “Correlator construction kit”, allowing numerical comparisons of correlator output and computing demands of different EVN network configurations
UMAN:
UORL:
KASI:
Problems / Issues
INAF reports a problem wrt funding. The engineer hired for the project is paid from local funds that will run out soon. Without a formal, signed, contract with the EC it will be hard to continue paying for this position.
Red flags - major problems
Forward Look (Q2-Q3)
ASTRON:
Start with PCB design (schematic)
Selection of FPGA vendor
Start exploring FPGA programming platform
Finalizing Schematic Start layout
Start Firmware design
BORD:
Detailed investigation of quantization effects to prepare VHDL coding using the mathematical model
VHDL coding (work shared with Arcetri)
Refined design document including study results (work shared with Arcetri)
INAF:
Design partitioning
Computer interface model for the instrument control/monitor
Refined design document including study results (work shared with BORD)
VHDL coding (work shared with BORD)
JIVE:
work on code for board testing (with ASTRON)
exploration of FPGA programming platform
start firmware design
choice of software platform for correlator control system
start design of correlator control system
UMAN:
UORL:
matlab simulation on real data (from Nancay telescope)
study of the current pulsar machine in collaboration with Manchester (specific meeting(s) are planned)
define the RFI mitigation algorithm architecture in collaboration with UMAN
Matlab model of this architecture
Test of this gold model on synthetic and real data
Expected milestones/ deliverables
Expenditures - equipment, material and services
In Q2 64 Altera Stratix IV FPGAs were ordered, as were 1 main and 2 companion 10GE IP licenses. Total amount involved $87680 for the FPGAs, $12500 for the licenses.
In Q3 several manufacturers will be asked for offertes on board production
Person months spent/to be spent until next EC Report (charged to EC)
Q1/Q2+Q3
ASTRON 1.2/6.6
BORD 0/6
INAF 1.8/9
JIVE 0/4
UMAN 0/1
UORL 1/2
Number of Persons working in JRA