UniBoard achievements in Q3

In spite of the vacation period in July and August, the UniBoard project progressed well during Q3. Two schematic review meetings were held, one internal at JIVE/ASTRON, with a number of local experts, followed by a review via videocon with all the partners. The layouting of the board is in full swing and firmware is being developed for testing purposes and to function as building blocks of the various applications. Design of a correlator control system has started and a project-wide SVN firmware repository has been created to enable the sharing of design among the partners. An MoU was agreed upon in which an extra payment, as subsidy towards the development of the UniBoard, will be made by all partners, prior to the actual production of the board. Finally, a board manufacturer has been selected. In all, the project is right on track, and we expect the first prototype at the end of 2009.

Documents:

• Erlang Part II: OTP mnsesia and the outside world, Des Small and Harro Verkouter, 01-07-2009
• PPT for Schematic Review Gijs Schoonderbeek, Sjouke Zwier, 07-07-2009
• UniBoard Schematic Gijs Schoonderbeek, Sjouke Zwier, 18-08-2009
• Evaluation of different options for the spectral domain data re-sampling for the VLBI application of the Uniboard, Sergei Pogrebenko, 19-08-2009
• Erlang demo: developing a realtime monitoring utility, Des Small and Harro Verkouter, 27-08-2009
• UniBoard PCB (preplacement) Sjouke Zwier / Gijs Schoonderbeek. 15-09-2009

General activities in Q3:

• Internal JIVE/ASTRON schematic review, 02-07-2009
• General schematic review per video conference, 10-07-2009
• 2-weekly general telecons

Activities by institute in Q3:

ASTRON:

• 2-weekly internal technical meetings
• schematic design finished
• board layout and routing started and ongoing production company selected
• with JIVE: firmware written to check all pinning
• in addition to listed documents, several documents produced on APERTIF beamformer and correlator system

BORD:

• continuing work on mathematical model to evaluate effects of filter weights and output signals from each module (polyphase filter and FFT)
• modification, simulation and validation of initial VHDL code produced by Arcetri for the polyphase filter block in the input FPGA
• T/H chips (65 nano technology) required for fast ADCs have been received from the foundry, test PCB has been designed

INAF

• refined conceptual design of the digital receiver filterbank, including input from modelling and board design
• draft computer interface model
• start of VHDL coding
• draft VHDL code for second stage digital filter
• resource estimate using simplified conceptual VHDL coding
• obtaining experience in the use of SOPC tools

JIVE:

• with ASTRON: completed set of designs to check schematic pinning designs to drive interfaces between FPGA and board: DDR3 memory, backplane, ADC, external and internal GX transceivers, 1 GbE control port I2C port
• with ASTRON: outline design for network control using the 1 GbE port and Nios embedded processor
• correlator control high level design started
• investigation into data formats

UMAN:

• engineer has been identified to work on pulsar aspects of development. This will focus on the development of the algorithm for coherent dedispersion and creating a model to convert this for use with the UniBoard
• discussions with UORL group has started regarding the interfaces between coherent dedispersion and interference rejection software
• video conference with UORL, July 10

UORL:

• video conference with UMAN, July 10
• Matlab simulation using real data (from Nancay telescope)

KASI:

• work had not started in Q3

Problems / Issues

Issues - organisational, administrative or other problems foreseen

• UMAN reports a problem with the long lead time in organising the funding

• INAF reports that the long lead time for personnel contracts in combination with the long delay in obtaining funding may cause discontinuities in the project

• Overall, it does not seem that the late payment of the pre-financing will cause a serious delay of the project.

• ASTRON/JIVE report a number of possible technical issues:

1) at this point, the full 40 Gbps interfaces of the front FPGAs can only be used with “soft cores” using up to 20% of all available logic. Hard cores are limited to 3 times 10 Gbps. From discussions with Altera representatives we understand that this problem will most likely be solved in the near future.

2) The “route space” between in and output FPGAs is limited, which may cause the speed between them to turn out lower than planned. This will have to be checked carefully once the first prototype has been produced.

3) the lead time of electronic components is longer than previously due to the economic situation. This is hopefully offset by the timely selection of a manufacturer.

Red flags - major problems

• none

Forward Look (Q4-Q7)

ASTRON:

• completion of PCB layout (Q4)
• production of first board (Q4-Q5)
• 7-board production run (Q6)

BORD:

• adaptation of various truncations used in system design based on model results (Q4-Q5)
• continuing simulation/validation of code produced at INAF
• adaption and addition to existing VHDL based on better definitions of interfaces and monitor points
• definition of ADC interface (Q4-Q5)

INAF:

• computer interface for instrument control/monitoring (Q4-Q5)
• refined design document based on study results (with BORD)

JIVE:

• detailed design of control interface (with ASTRON) (Q4)
• FPGA designs to test first board and control interface verification correlator mapped out (with ASTRON) (Q4)
• board testing (with ASTRON) (Q5)
• writing of main components of correlator design, including packet receiver/sorter, delay module, filter bank/FFT, correlation engine and processed data output (Q5-Q6)
• reformatting exising dataformats to single-channel, single-data-thread VDIF format (Q4)
• design main database scheme for the correlator control system: all components read setting/write status|statistics in this. Will be initialized from VEX files (Q5)
• correlate existing data (from file) with the JIVE software correlator, controlled from/by the correlator control software (Q6-Q7)

UMAN:

• face-to-face meeting with UORL group in Manchester (Q4)
• depending on start date of engineering effort:

Algorithm modeling Algorithm Implementation & Test Hardware Test

UORL:

• face-to-face meeting with UORL group in Manchester (Q4)
• continuing matlab simulations on real data from Nancay telescope
• definition of RFI mitigation algorithm architecture with UMAN (Q5)
• matlab model of this architecture (Q6)
• test of gold model on synthetic and real data (Q6)
• VHDL coding (Q7)

KASI:

• one KASI engineer will visit JIVE/ASTRON in Q5, to assist in hardware tests

Expected milestones/ deliverables

• hard and firmware design documents, month 11